1. Field of the Invention
The present invention generally relates to pattern-evaluation aiding devices and methods, and more particularly relates to a pattern-evaluation aiding device and a method which can emulate signal patterns appearing on lines connecting nodes of devices implemented on a circuit board.
2. Description of the Prior Art
Many electronic devices contain multi-chip modules or printed boards on which IC chips are implemented and connected with each other. Also, such large devices as transfer devices contain a plurality of modules connected with each other via connecters, whose pins are connected together through lines formed on a mother board.
On a multi-chip module board, a printed board, or a mother board (hereinafter, these are collectively called a circuit board), a wiring pattern is formed to provide lines which connect devices with each other and also with input/output nodes.
Characteristic impedances of such lines need to match impedances of devices connected thereto, otherwise signal reflections may appear at nodes of these devices. However, typical pattern designing processes do not take into account such impedance matching for all nodes connected to a wiring pattern. This is because a scope for designing the wiring pattern is usually restricted by a size and a shape of the circuit board, and also because impedance mismatches between a plurality of devices make it difficult to cope with all the nodes. In the designing of the wiring pattern, also, certain requirements are regarded to be more important than a requirement for the impedance matching, such requirements including the use of pattern-designing processes of a standard type and the use of lines having a uniform thickness on a circuit board. Thus, it is not common to use a pattern-designing technique which forms lines of varying widths and varying cross-sectional areas for achieving the impedance matching.
FIG. 1 shows an illustrative drawing showing an example of signal reflections between two devices. As shown in FIG. 1, a signal sent by a driving device 91 is propagated on a wiring pattern 92 on a circuit board 94 to reach an input node of a driven device 93. Since an input impedance of the driven device 93 does not match a characteristic impedance of the wiring pattern 92, the signal is reflected at the input node of the driven device 93. Further, the reflected signal is again reflected at an output node of the driving device 91. That is, signal reflections are repeated between those two devices via the wiring pattern 92. Hereinafter, the signals reflected back and forth on the wiring pattern are referred to as reflected signals.
FIG. 2 is a graph showing voltage level changes at the output node of the driving device 91 and at the input node of the driven device 93. In FIG. 2, the voltage level at the input node of the driven device 93 has a temporal variation shown by dotted lines. When the driving device 93 is a digital device showing a strong impedance mismatch, the voltage level at the input node can have a variation of a large magnitude. As a result, the voltage level at the input node may go below a threshold voltage level Vth of the device, thus creating a malfunctioning case.
In the prior art, methods for avoiding such a malfunction include making a rough estimate of a number of repetitions, by which number of repetitions reflected signals on a wiring pattern between devices converge into a stable signal. The rough estimate of this number is conventionally made by assuming the same number of repetitions for all the paths on the wiring pattern, thus ignoring individual differences in impedances between different paths and different devices. Then, a delay time necessary for signals to become stable is obtained by multiplying a delay time of the wiring pattern by the number of repetitions estimated above. The delay time thus obtained is optimum in a sense that this is the shortest time period for achieving the stable signal on the wiring pattern. Then, an optimal arrangement of the wiring pattern and the devices is designed by using the optimum delay time obtained above.
In the prior art method described above, however, the estimate of the repetition number is based on an assumption which ignores the impedance differences between the devices and the paths. As a result, a truncation error owing to the use of the finite number of repetitions can become too large to be ignored in some cases. Thus, enough precision cannot be achieved which is required for a complex wiring pattern used in highly sophisticated electronic devices.
Furthermore, circuits operating at high speed demand a small delay time for each device. Thus, such circuits should be evaluated more precisely prior to the manufacturing of the circuits as to whether they can stably operate within established parameters.
Accordingly, there is a need in the field of pattern evaluation for a pattern-evaluation aiding device and a method which can emulate signal patterns on a wiring pattern with an increased precision.